1. Field of the Invention
The present invention relates to a synchronous logic data latch apparatus, which can be incorporated in a synchronous semiconductor memory device (DRAM).
2. Description of the Related Art
In a prior art logic data latch apparatus which is used in a synchronous DRAM, logic signals or control signals such as a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE and a chip select signal CS are latched in latch circuits in synchronization with a rising edge of a system clock signal from the exterior. In this case, a set up time T.sub.S of the logic signals with respect to the rinsing edge of the system clock signal is on the order of nano seconds, and a hold time T.sub.H of the logic signals with respect to the rising edge of the system clock signal is also on the order of nano seconds. In this case, the margin of the set up time T.sub.S and the margin of the hold time T.sub.H are small. Then, the output signals of the latch circuits are supplied to logic circuits which, in turn, generate various internal control signals. This will be explained later in detail.
In the above-described prior art logic data latch apparatus, however, use is not made of the set up time T.sub.S. As a result, the transfer rate of data is decreased by the system clock signal. This decreases the access speed of the apparatus.
Also, in the above-described prior art apparatus, since there may be a skew between the output signals of the latch circuits, hazard (distortion errors) may be generated in the output signal of the logic circuit.